Index

B

blackbox

C

core area

CTS CVC

D

decap DFT

die area DRC DV

E

endcap

F

Floorplan

G

GDSII

GL

H

harden

HDL

I

IP

L

LEC

LVS

M

magic

O

OpenLane

openroad

P

Parasitic Extraction

PDK Placement

R

RTL

S

signoff

SPEF STA

T

The OpenROAD Project

tie cell

V

Verilog

VHDL Volare

W

welltap

Y

Yosys