This page describes terms that are used in the Ordie project, as well as in open silicon and IC design.
OpenROAD is the umbrella project that brings together various open silicon tools and projects to go from RTL to GDS.
A product produced by the OpenROAD project that incorporates floorplanning, placement, cts, optimization, and global routing. Used as part of the OpenLane flow.
A full, end-to-end set of scripts that can be used to generate GDSII files from HDL. OpenLane is the entire “toolchain” that bundles all other projects together and supports running them in sequence. OpenLane consists of TCL and Python scripts that glue all of the other projects together.
Hardware Definition Language. A language such as VHDL or Verilog that can be used to describe hardware. Produces RTL when synthesized.
Register-Transfer Level. The logical circuit and state machine formed by synthesizing HDL. RTL is sometimes referred to as IP.
A Hardware Definition Language that vaguely resembles Pascal.
A Hardware Definition Language that vaguely resembles Ada.
Yosys is a synthesis program which takes input such as Verilog code as well as primitives for a particular backend and generates outputs that can be fed into a tool for further processing. As an example, Yosys might turn a statement that adds two registers together into a series of LUT4 adders that exist on a particular FPGA or PDK. Yosys will not do any sort of physical cell placement or routing, it will simply turn Verilog code into RTL.
Process Design Kit. The set of primitives and design rules available on a certain foundary’s process node. A PDK may include basics such as NAND and NOR gates, transistors, FETs, capacitors, and resistors, and it may include more advanced cells such as RAMs and fuses.
Also called GDS2 or simply GDS, this is the de-facto industry standard for submitting chip designs. It can be thought of as the “Gerber” equivalent for chips. Note that GDSII supports “black boxes” where the foundary is directed to add their own IP blocks.
The industry term for an existing design, originally standing for “Intellectual Property”. An IP core can be thought of as a library that is added to a chip design. For example, you may add I2C IP in order to allow your design to communicate using that bus.
Static Timing Analysis. This step in the synthesis flow determines how fast a circuit can run, and whether it can meet the frequency required by the designer.
Design For Testing. This step adds features to the chip that can be used for diagnostics, such as scan chain insertion. This allows for the designer to probe various sections of the chip once it has been built.
An initial arrangement of various sections on the chip. Floorplans are rough guides that are used to plan the rest of layout. For example, bond pads may be placed at the edges early on in the floorplanning process.
Placement involves assigning cells their physical (X, Y) coordinates. Placement does not do any routing.
Clock Tree Synthesis. This runs wires for the clock tree, adds buffers as necessary, and tries to keep latency and skew within acceptable parameters. This step comes immediately after the placement step, because clock resources are so important to keeping the chip synchronized.
Circuit Validity Check. Ensures that the circuit does not have any errors such as signals crossing voltage domains, leaks due to intermittent floating inputs, or errors due to cutoff regions.
Parsitic Extraction involves creating an analogue model of the chip that can be used for simulation.
Standard Parasitic Exchange Format. A file format that describes parasitics, and is the result of Parasitic Extraction.
Logic Equivalency Check. This optional step ensures that the logic of the generated chip matches the original HDL. This step takes a very long time, and is usually omitted except for the final tapeout step.
A tool to manage installed PDKs, as well as a repository of prebuilt PDKs.
The process of turning RTL and other “soft” source design files into GDSII. A hardware equivalent of “compiling”.
magic is a tool used to edit raw GDSII files. It is also capable of running DRC and antenna checks on the final product.
Design Rule Check. A PDK has a number of design rules that indicate a wide number of rules such as minimum trace width, minimum spacing between two features, or minimum angle when routing edges. A DRC check ensures that the design meets these rules.
Layout Vs Schematic. This check ensures that the chip, as it was laid out, matches the schematic that did the layout. This step essentially reverse-engineers the chip and builds a netlist from the components it sees, then compares that netlist to the one that was used to generate the chip.
The process of verifying the resulting design meets the rules set forth by the PDK and, when manufactured, will function as intended.
The size (in um) of the die to be generated.
The size (in um) of the available space to place features. This is equal to the die area minus the required margins.
A tie cell is a cell that buffers either the high or low voltage rail when connecting to a transistor that is tied high or low. This prevents surges from damaging the polysilicon gate.
A welltap is a generated structure that is placed at regular intervals around the chip in order to ensure that voltage rails are consistent. Well taps (or well tap cells) tie the nwell to VDD and the p-substrate to VSS / GND.
An endcap cell exists to pad out different IP blocks in order to ensure they don’t couple. Endcap cells act as a border between different areas of the chip.
A decap cell is one that is inserted in order to prevent coupling between VDD and VSS.
An IP block that exists as just some GDSII plus a representation in HDL. A blackbox may be some proprietary block where you don’t have the source code, or it may be a macro such as a RAM block where you pre-route a subsection of the chip in order to speed up hardening.
Design Verification. A series of files that can be used to simulate the final design, either as a testbench that can be used with a simulator or as C code that emulates the final target.
Gate-level Verilog. This is the output of design synthesis, and is a one-to-one mapping of logic gates to hardware. When simulating the final design, it is desirable to use gate-level verilog to ensure there are no synthesis bugs.