Welcome to Ordie: The Primordial Microcontroller’s documentation!

Contents:

• Introduction
  • Hardening Steps
• Prerequisites
• Creating a Python venv
• Installing Required Software
  • Magic
  • OpenROAD
  • OpenLane
  • Yosys
  • KLayout
  • netgen
  • Circuit Validity Checker
• OpenRAM
• PDK
  • Prebuilt PDK
  • Assemble the PDK
• Hardening Overview
  • Synthesis
  • Floorplanning
  • Placement
  • Clock Tree Synthesis
  • Routing
• Running the hardening flow
• Important settings
  • Selecting a Density
  • Defining the default GPIOs
• Memory and Memories
  • OpenRAM
  • DFFRAM
  • Creating a new DFFRAM entity
• Solving Common Problems
  • Synthesis Takes a Very Long Time
  • Unable to Place Design
  • Unable to Route Design
  • Setup Violation
  • There are violations in the design after detailed routing
  • git push: … this exceeds GitHub’s file size limit of 100.00 MB
  • There are LVS errors in the design
  • There are hold violations in the design at the typical corner
• Walkthrough
• Glossary

Indices and tables

• Index

• Module Index

• Search Page